In a pipeline processing architecture, tasks to be performed on a data unit are broken into component operations. A pipeline processor includes of a number of hardware or software processing entities, where each processing entity is configured to perform one or more of the component operations and to pass a data unit to a next processing entity upon completion of a component operation. Thus, a first processing entity in a pipeline passes the results from performing its component operation on a first data unit to a downstream processing entity in the pipeline. The first processing entity then begins performing its component operation on a second data unit while the downstream processing entity operates on the results received from the first processing entity. In this manner, with different data units being simultaneously processed at different processing entities in the pipeline, at any given time the pipeline operates on multiple data units that are passing through the pipeline. Consequently, because each data unit is passed through every processing entity in the pipeline, each data unit is processed in the pipeline for the same amount of time regardless of its actual processing requirement.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.